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- // ============================================================
- // Shared Parameters
- // include <params.scad> in all component files
- // ============================================================
- /* [Design Style] */
- EPD_IS_LID = true; // true: epd_case forms the lid ceiling; false: flat ceiling plate
- /* [Shared Case] */
- WALL = 2.0;
- CORNER_R = 2.5;
- /* [Display Dimensions — GDEY0583T81] */
- DISP_W = 125.4;
- DISP_D = 99.5;
- DISP_T = 1.2;
- ACT_W = 118.78;
- ACT_D = 88.22;
- /* [EPD Case Parameters] */
- LIP = 1.5;
- TOL = 0.3;
- CHAM = 1.0;
- CHAM_ANGLE = 60;
- BEZEL_Y = 2.5;
- FPC_BEND_R = 4.0;
- /* [EPD Case Derived] */
- epd_cav_w = DISP_W + TOL * 2;
- epd_cav_d = DISP_D + TOL;
- epd_case_w = epd_cav_w + WALL * 2;
- epd_case_h = WALL + DISP_T + LIP;
- _fpc_x1 = WALL + TOL + DISP_W - 55.47 - 12.50 - 2.5;
- _fpc_xw = 12.50 + 5.0;
- _fpc_ro = FPC_BEND_R + 0.30 + TOL;
- _bend_my = BEZEL_Y + DISP_D + sqrt(_fpc_ro*_fpc_ro - (FPC_BEND_R - WALL)*(FPC_BEND_R - WALL));
- epd_case_d = max(epd_cav_d + WALL + BEZEL_Y, _bend_my + WALL);
- _cham_xy = CHAM * tan(CHAM_ANGLE);
- epd_win_x = WALL + TOL + (DISP_W - ACT_W) / 2;
- epd_win_y = 3.30 + BEZEL_Y;
- /* [Board Dimensions — EE04] */
- PCB_L = 80.00;
- PCB_W = 41.22;
- PCB_T = 1.93;
- COMP_MAX_Z = 7.29;
- COMP_SIDE_Z = 3.82;
- /* [Sliding Lid] */
- LID_T = 1.5;
- FLANGE_H = 3.0;
- FLANGE_W = FLANGE_H * tan(30);
- SLIDE_CLEAR = 0.40;
- /* [FPC Notch — must match EPD case slot geometry] */
- FPC_NOTCH_W = _fpc_xw; // slot X width: cable 12.5 + 2×2.5 mm clearance
- FPC_U_T = LID_T;
- FPC_SLOT_W = 4.1; // ≈ sqrt(_fpc_ro²−(FPC_BEND_R−WALL)²) at epd_case z=0
- /* [+Y Wall Cutouts] */
- PWR_CX = 10.3;
- PWR_W = 5.0;
- PWR_H = 2.5;
- PWR_CZ = 3.8;
- PWR_COVER_T = 0.6;
- USBC_CX = 65.65;
- USBC_W = 9.0;
- USBC_H = 3.22;
- USBC_CZ = 4.31;
- USBC_CBL_CLEAR = 1.5;
- BTN_CX = [48.4, 39.075, 29.725, 20.425];
- BTN_D = 2.3;
- BTN_CZ = 3.85;
- /* [Plunger] */
- PLUNGER_D = 2.0;
- FLANGE_D = 2.9;
- FLANGE_T = 1.2;
- PLUNGER_HEAD_H = 1.5;
- /* [CPU Case] */
- FLOOR = 2.0;
- SCREW_D = 3.2;
- BOSS_D = 6.0;
- BOSS_H = 2.0;
- /* [Locating Studs] */
- STUD_CLEAR = 0.10;
- STUD_H = PCB_T + 1.0;
- STUD_R = (SCREW_D - 2*STUD_CLEAR) / 2;
- /* [PCB Standoff Positions — relative to PCB origin] */
- PCB_BOSS_X1 = 2.5;
- PCB_BOSS_X2 = PCB_L - 2.5;
- PCB_BOSS_Y1 = 2.5;
- PCB_BOSS_Y2 = PCB_W - 2.5;
- /* [Interior Clearances] */
- CLR_XN = 2.0;
- CLR_XP = 44.0;
- CLR_YN = 15.0;
- CLR_YP = 1.77;
- CLR_LID = 3.5;
- BATT_W = 34.5;
- BATT_D = 51.0;
- BATT_T = 6.3;
- CLR_BATX = 1.5;
- CLR_BATY = 1.5;
- /* [CPU Case Derived] */
- PCB_Z = FLOOR + BOSS_H;
- BASE_INNER_H = BOSS_H + COMP_MAX_Z + CLR_LID;
- BASE_H = FLOOR + BASE_INNER_H;
- PCB_OX = WALL + CLR_XN;
- PCB_OY = WALL + CLR_YN;
- CAV_L = CLR_XN + PCB_L + CLR_XP;
- CAV_W = CLR_YN + PCB_W + CLR_YP;
- OUT_L = CAV_L + 2*WALL;
- OUT_W = CAV_W + 2*WALL;
- LID_H = FLANGE_H + LID_T;
- LID_Y_LEN = CAV_W;
- // FPC alignment — derived from EPD case geometry (replaces hardcoded values in old cpu_case)
- FPC_CX = OUT_L/2 - epd_case_w/2 + (_fpc_x1 + _fpc_xw/2) - PCB_OX;
- FPC_U_DEPTH = FPC_U_T - WALL - 3 + (epd_case_d - (BEZEL_Y + DISP_D));
- /* [Shared Helper] */
- module rounded_box(l, w, h, r) {
- hull()
- for (dx = [r, l-r], dy = [r, w-r])
- translate([dx, dy, 0]) cylinder(r=r, h=h, $fn=32);
- }
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